[PATCH 2/8] ARM: Implement read/write for ownership in theARMv6 DMA cache ops

[Ronen Shitrit]

-----Original Message-----
From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] 
Sent: Monday, May 17, 2010 10:43 AM
To: Ronen Shitrit
Cc: Catalin Marinas; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 2/8] ARM: Implement read/write for ownership in theARMv6 DMA cache ops

On Mon, May 17, 2010 at 10:34:36AM +0300, Ronen Shitrit wrote:
> After some more thinking, I think I found the problem...
> 
> DMA for receive should operate as follows:
> 1) CPU will map (invalidate) the buffers for the DMA
> 2) DMA will place the buffers and ack the CPU
> 3) The CPU will call unmap which will invalidate the buffers again
> 
> 
> I can only think of one problematic scenario:
> - After 1 and before 2: 
> 	CPU0 did spec prefetch for address x 
> - After 2: 
> 	CPU0 is doing inv: lock int, ldr x, 
> 		str x (addr x is marked dirty with wrong data).

The data has been corrupted at this point; you don't need a second CPU.
[Ronen Shitrit] Why? If the second CPU doesn't exist an invalidate will come just after the str inst and the wrong data will not get anywhere... (interrupts are locked so I assume no eviction...)

> 	CPU1 at this time doing spec prefetch for x which 
> 		will snoop CPU0 and will cause data corruption... :(
> 
> I can assume that if I count on the Soc IO cache coherency support all
> this isn't relevant, right? Or there are some issues hiding with v6 +
> IO coherency?

What "IO cache coherency" ?  Are you saying that your SoC has a mode
where the DMA controller can snoop the CPU caches?


[Ronen Shitrit] Yes. 
I also found that I can disable D-cache spec prefetch.
However I-cache prefetch still exist and we have unified shared L2, so I think the ldr/str WA is still not valid since it might load garbage from the L2 as a result of I-cache spec pref... right?


I guess that for machines that has only I-cache spec pref, unmap should invalidate only the unified caches (in my case the L2).
And for machines that has also D-cache spec pref, unmap should invalidate all caches.