PIPT cache handling on s5pv210 chip

[Russell King - ARM Linux]

On Fri, May 14, 2010 at 07:36:47PM +0900, Kukjin Kim wrote:
> In case of __vmalloc() with non-cacheable option, there may come some
> malfunctions related to cache.

Practically, you are not allowed on ARMv6 or ARMv7 to create mappings
which alias with differing memory types; that is 100% outlawed by the
architecture spec, and there is NO mitigation for this.

It means that it is _illegal_ to use __vmalloc() with anything but a
memory-like mapping protection.

There is mitigation for having different cacheability, but this is just
a work-around while OSes like Linux work to remove the creation of
aliases with differing cacheability attributes.  There's no guarantee
that later ARMv7 or future CPUs will continue to operate predictably.

The same applies for ioremap() being used on SDRAM - and those who look
at what's in my tree will notice that ioremap() has recently been made
to fail when used on SDRAM for this very reason.

Therefore, the above hack isn't going near mainline.