[BUG] bug when enabling VM DEBUG
catalin.marinas at arm.com
Thu May 13 07:30:33 EDT 2010
On Wed, 2010-05-12 at 14:06 +0100, Jamie Lokier wrote:
> Catalin Marinas wrote:
> > On Wed, 2010-05-12 at 12:53 +0100, Sebastian Andrzej Siewior wrote:
> > > * Catalin Marinas | 2010-05-12 12:10:39 [+0100]:
> > >
> > > >> > --- a/drivers/ata/libata-sff.c
> > > >> > +++ b/drivers/ata/libata-sff.c
> > > >> > @@ -894,7 +894,7 @@ static void ata_pio_sector(struct ata_queued_cmd *qc)
> > > >> > do_write);
> > > >> > }
> > > >> >
> > > >> > - if (!do_write)
> > > >> > + if (!do_write&& !PageSlab(page))
> > > >> > flush_dcache_page(page);
> > > >>
> > > >> I would think that check belongs inside flush_dcache_page itself, rather
> > > >> than forcing every driver to include it..
> > > >
> > > >Sebastian (cc'ed) reported this as well for MIPS.
> > > Thx. The patch above looks what I've sent a while ago. Jeff was going to
> > > merge it afaik.
> > >
> > > >I think it makes sense for this check to be done in the
> > > >flush_dcache_page() function.
> > >
> > > Why should flush_dcache_page() not flush pages you tell it?
> > > From Documentation/cachetlb.txt:
> > > | NOTE: This routine need only be called for page cache pages
> > > | which can potentially ever be mapped into the address
> > > | space of a user process. So for example, VFS layer code
> > > | handling vfs symlinks in the page cache need not call
> > > | this interface at all.
> > >
> > > A page from slab or stack is not going to see the sky of user land and
> > > therefore it should not be fed into flush_dcache_page().
> > You are right :), so fixing the driver is the best approach.
> It worries me that a driver has any knowledge of the PageSlab() flag,
> though. Especially uncommented knowledge. That flag seems VM
> internal, and it's conceptually iffy: Kernel code using
> get_free_pages() and using that for I/O also does not see the sky of
> user land.
> If all the PIO drivers have to be changed, I'd be happier with:
> which wraps the check, explains it, and provides a single place to
> change if needed.
I already proposed a PIO cache flushing API on linux-arch. I tried to
revive the discussion with another patch for cachetlb.txt but it hasn't
drawn much interest.
On ARM we are trying to change the I/D cache handling similar to IA-64
and PowerPC (PG_arch_1 would mean "clean" rather than "dirty"). With
this change, my original patch to libata-sff.c can be dropped (well,
other architectures may still be broken).
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