Rampant ext3/4 corruption on 2.6.34-rc7 with VIVT ARM (Marvell 88f5182)
benh at kernel.crashing.org
Thu May 13 00:42:31 EDT 2010
On Thu, 2010-05-13 at 12:12 +0900, FUJITA Tomonori wrote:
> X86 OOSTORE uses a memory barrier dma_sync_single_for_device (seems
> that some mips archs also use it and do cache operations).
> I think that the DMA-API says that
> - dma_sync_single_for_device() makes sure the data ready for DMA.
> - dma_sync_single_for_cpu() makes sure that drivers doesn't get the
> stale data after DMA.
> I guess, it means if an architecture need a memory barrier (not only
> cache operations) to guarantee the above, the architecture needs to
> take care of it.
Right, but doing an indirect function pointer call for a memory barrier
in what can be a pretty hot code path doesn't sound like a great idea
if it can be avoided. I'd rather we define some inline that the arch
can stick in there if it wishes so.
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