catalin.marinas at arm.com
Wed May 12 17:39:54 EDT 2010
On Wed, 2010-05-12 at 19:42 +0100, Russell King - ARM Linux wrote:
> On Wed, May 12, 2010 at 12:18:40PM +0100, Catalin Marinas wrote:
> > For non-aliasing VIPT hardware we still have the option of doing what
> > the IA-64 and PowerPC guys have done (flushing in set_pte_at with
> > PG_arch_1 meaning "clean"). It may even work for VIVT caches if we take
> > care to also flush the kernel alias in set_pte_at.
> It should work for VIVT as well, so lets just go ahead and negate the
> PG_arch_1 meaning. I was rather expecting this to be done a month or
> so ago while we still had plenty of time before the next merge window -
> and given where we are now (maybe 2 weeks away) I think it's too risky
> to push into the upcoming window.
Well, I started and then I had to go on holiday (and drive back ~1500
miles because of the volcanic ash).
> I'm already planning on scheduling the ioremap and LMB changes for the
> following window, and I think this should be scheduled likewise.
The cache flushing change would need some wider testing, so maybe 6-8
weeks should be enough. I'll try to get some rfc patches by the end of
> > If you are ok with this approach, I'll prepare some patches (it seems
> > that trying to get an agreement with other architectures isn't very
> > productive).
> That's what I've always found with this issue; whenever I've talked
> with the mainline community about PIO cache coherency, the result has
> always been non-productive. Hence why it's always remained a problem
> for us.
The good thing is that I found out how PowerPC deals with it :)
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