[PATCH 2/8] ARM: Implement read/write for ownership in the ARMv6 DMA cache ops
rshitrit at marvell.com
Wed May 12 16:00:42 EDT 2010
This is a good point, assuming the patch will lock the int a round the
dma cache calls, can you think of any data coruption issues?
Sent from my phone
On 12/05/2010, at 21:59, "Russell King - ARM Linux" <linux at arm.linux.org.uk
> On Wed, May 12, 2010 at 07:48:52PM +0100, Russell King - ARM Linux
>> Aren't there CPUs which speculatively prefetch _and_ which don't have
>> broadcast cache ops? If yes, then we can't use the "read/write to
>> gain ownership" approach - and since we can't use IPIs either, I
>> we're sadly boxed in by hardware restrictions to the point of not
>> able to run with DMA on these CPUs.
> I just had a second thought that what I wrote above was tosh, but then
> had a third thought which reconfirmed it as a valid point...
> Consider if the CPU speculatively prefetches the line you're going to
> read before the DMA has completed, and it prefetches the pre-DMA data.
> Your read loads the pre-DMA data, and the write writes it back to the
> cache line. An interrupt happens, and the cache line gets evicted
> time later before the invalidate line operation - overwriting the DMA
> data, thereby corrupting it.
> So, a CPU which speculatively prefetches _and_ doesn't broadcast cache
> operations _is_ a big problem. I hope we don't have any.
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