[PATCH 1/5] ARM: Use lazy cache flushing on ARMv7 SMP systems
catalin.marinas at arm.com
Fri Mar 26 10:49:42 EDT 2010
On Tue, 2010-03-23 at 21:33 +0000, Russell King - ARM Linux wrote:
> On Mon, Mar 22, 2010 at 03:19:39PM +0000, Catalin Marinas wrote:
> > ARMv7 processors like Cortex-A9 broadcast the cache maintenance
> > operations in hardware. This patch allows the
> > flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
> > similar to the UP case.
> Didn't Ben point out that there's a race with the lazy dcache flushing
> on SMP platforms?
BTW, even with the current code we still have a similar race with the
I-cache. set_pte_at() creates the entry that another CPU may execute
from before we invalidate the I-cache in update_mmu_cache().
A solution would be that set_pte_at() sets the NX bit which is cleared
later in udpate_mmu_cache() after the I-cache invalidation. Some care
needs to be taken with possible prefetch aborts in the small window when
the page isn't executable.
Note that even if we flush the caches in set_pte_at(), we still have the
I-cache race unless we write the pte twice, first with NX and then
without. So I'm more in favour of the solution in the previous
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