USB mass storage and ARM cache coherency
oliver at neukum.org
Sat Mar 6 06:05:17 EST 2010
Am Samstag, 6. März 2010 11:56:41 schrieb Wolfgang Mües:
> > 1. A page is faulted in for an application, and it is a text page.
> > - the data read in to the page needs to be visible to the instruction
> > stream, so on Harvard architecture machines, this may require cache
> > maintainence on both the D and I caches.
> Yes. I think that the EXPECTED behaviour of block devices is to give the
> result of the read back in memory. So the driver should do the flush of the
> data cache.
> The invalidation of the I cache should be done by the function which makes
> this piece of data executable. (Have I missed something here?)
What tells you that IO is happening before the page is made executable?
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