No subject

used loops that counted udelay(1) I've noticed that the
PLLE_MISC_READY is set after up to 3usecs.

> <snip>
>
>> +static struct clk_ops tegra_pcie_clk_ops =3D {
>> + =A0 =A0 =A0 .enable =A0 =A0 =3D tegra2_periph_clk_enable,
>> + =A0 =A0 =A0 .disable =A0 =A0=3D tegra2_periph_clk_disable,
>> +};
> Why is this needed? =A0Won't the regular periph ops work?

They didn't. I haven't found anything about what feeds these clocks,
can they change rate, what clock can be their parent and if there is
any muxing options for these clocks.

> <snip>
>
>> +static struct clk tegra_clk_pex =3D {
>> + =A0 =A0 =A0 .name =A0 =A0 =A0=3D "pex",
>> + =A0 =A0 =A0 .flags =A0 =A0 =3D PERIPH_MANUAL_RESET,
>> + =A0 =A0 =A0 .ops =A0 =A0 =A0 =3D &tegra_pcie_clk_ops,
>> + =A0 =A0 =A0 .clk_num =A0 =3D 70,
>> +};
>> +
>> +static struct clk tegra_clk_afi =3D {
>> + =A0 =A0 =A0 .name =A0 =A0 =A0=3D "afi",
>> + =A0 =A0 =A0 .flags =A0 =A0 =3D PERIPH_MANUAL_RESET,
>> + =A0 =A0 =A0 .ops =A0 =A0 =A0 =3D &tegra_pcie_clk_ops,
>> + =A0 =A0 =A0 .clk_num =A0 =3D 72,
>> +};
>> +
>> +/* the pcie_xclk is required for reset of PCIE subsystem */
>> +static struct clk tegra_clk_pcie_xclk =3D {
>> + =A0 =A0 =A0 .name =A0 =A0 =A0=3D "pcie_xclk",
>> + =A0 =A0 =A0 .clk_num =A0 =3D 74,
>> +};
> These should probably all be defined in the CLK_PERIPH table.

See the comment above :)

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--=20
=A0 =A0 Sincerely Yours,
=A0 =A0 =A0 =A0 Mike.