[PATCH] S5PV210 Correct clock register properties
Kukjin Kim
kgene.kim at samsung.com
Thu Jun 17 22:38:04 EDT 2010
MyungJoo Ham wrote:
>
> From: MyungJoo Ham <myungJoo.ham at samsung.com>
>
> Corrected shift values of I2S and UART clocks (CLK_GATE_IP3).
>
> I2S (CLK_GATE_IP3) and UART (CLK_GATE_IP3) had wrong register shift
> values, which in turn, made them turn on and off wrong clocks.
(snip)
Sorry..kindly ignore below comments.
My mistake..
---
Your point is right..but your updated code was wrong :-(
Should be like below.
@@ -400,19 +400,19 @@ static struct clk init_clocks_disable[] = {
.id = 0,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1<<4),
+ .ctrlbit = (1 << 4),
}, {
.name = "i2s_v32",
.id = 0,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1<<4),
+ .ctrlbit = (1 << 5),
}, {
.name = "i2s_v32",
.id = 1,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
- .ctrlbit = (1<<4),
+ .ctrlbit = (1 << 6),
---
(snip)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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