facing undefined inconsistent cache issues on cortex-a9

[Woodruff, Richard]

> From: Shiraz HASHIM [mailto:shiraz.hashim at st.com]
> Sent: Friday, June 04, 2010 8:55 AM
> To: Woodruff, Richard

> thanks for your inputs. We have some updates in this regard.
> In our architecture we have 2 ports coming out of the A9SM (multi core cortex)
> block to the interconnect matrix and the transfers are distributed between
> them.
>
> When we used the address filtering option of SCU to divide and mutually
> exclude
> the traffic between port0 and port1 of A9SM(multi core cortex) block. Like,
> assigning 1 half of the address space to port 1 and rest goes through port0.
> This solved the problem with the same set of cache and other system
> configurations.
> We are not using L2 cache and it is kept disabled. The SCU also is only used
> for
> address filtering and its synchronisation function is disabled (as we are not
> bringing up the second core)
> Now, we are not able to understand what it means. Do we need to divide the
> traffic between ports as described and it is normal. Or there is some problem
> in
> the way the transfers are handled in the system.

Off hand I'm not sure of the right answer.  The design I'm working on does not require the filtering feature so I've not looked much at it outside of some errata.  I am aware of another design which accesses a bit larger address space which does use filtering.

I'd guess you need to understand your cortex-memmap + AXI-to-memory bus adapter characteristics.

Regards,
Richard W.