[PATCH v2 1/3] ARM: Introduce *_relaxed() I/O accessors

[Catalin Marinas]

On Mon, 2010-07-12 at 13:46 +0100, Jamie Lokier wrote:
> Catalin Marinas wrote:
> > On Mon, 2010-07-12 at 12:50 +0100, Jamie Lokier wrote:
> > > Arnd Bergmann wrote:
> > > > Ah, that's right: writel and outl both need the barrier before the access,
> > > > but writel will never need a barrier after the access.
> > > > The x86 variant of outl also has the implicit ordering after the access,
> > > > but I'm not sure if we need to emulate that. I can't currently think
> > > > of a case where it's strictly required because any later access to the same
> > > > PCI function will be ordered anyway.
> > >
> > > What about those ARMs which can buffer a write for an indefinite period?
> > > Do any drivers expect writes to be posted in a reasonably short time?
> >
> > Writing to any device is not guaranteed to succeed (i.e. change the
> > state of the device) in a certain amount of time (this is probably the
> > case on x86 as well). If you need this certainty in the code, you do a
> > read back from the device. Since Device memory accesses are ordered in
> > ARM, we don't need additional barriers for such situations.
> 
> There's a time between a "certain amount" and "infinite".
> 
> I'm pretty sure the write buffering time for x86 is guaranteed to be
> finite and quite short (without specifying exactly how short - just
> like instructions don't specify how long they take to execute), as in
> it's just a buffer, whose delay is a similar order of magnitude to bus
> transactions.  It's not a cache.
> 
> A recent commit changes ARM cpu_relax() because it can keep writes
> buffered indefinitely.  The commit message does say it's because reads
> are prioritised over writes, so perhaps that's only an issue in loops
> which use cpu_relax() anyway.

That was an issue visible on ARM11MPCore. On ARMv7 cores, it is
mandatory for the write buffer to drain in a finite amount of time
(though I'm not sure how long this could be). The cpu_relax() problem
that we've seen won't happen on ARMv7 cores. Pre-v6 processors have a
stronger memory order model, especially in relation to uncached DMA
buffers.

-- 
Catalin