[PATCH v2 1/3] ARM: Introduce *_relaxed() I/O accessors

[Catalin Marinas]

On Mon, 2010-07-12 at 12:50 +0100, Jamie Lokier wrote:
> Arnd Bergmann wrote:
> > Ah, that's right: writel and outl both need the barrier before the access,
> > but writel will never need a barrier after the access.
> > The x86 variant of outl also has the implicit ordering after the access,
> > but I'm not sure if we need to emulate that. I can't currently think
> > of a case where it's strictly required because any later access to the same
> > PCI function will be ordered anyway.
> 
> What about those ARMs which can buffer a write for an indefinite period?
> Do any drivers expect writes to be posted in a reasonably short time?

Writing to any device is not guaranteed to succeed (i.e. change the
state of the device) in a certain amount of time (this is probably the
case on x86 as well). If you need this certainty in the code, you do a
read back from the device. Since Device memory accesses are ordered in
ARM, we don't need additional barriers for such situations.

-- 
Catalin