amba clcd clock/timing check mismatch

[Russell King - ARM Linux]

On Wed, Aug 18, 2010 at 05:23:56PM -0700, Kevin Wells wrote:
> On Tue, Aug 17, 2010 at 10:27 AM, Kevin Wells <wellsk40 at gmail.com> wrote:
> >>> >From the include/linux/amba/clcd.h file, in the clcdfb_check() function...
> >>>
> >>> #define CHECK(e,l,h) (var->e < l || var->e > h)
> >>>       if (CHECK(right_margin, (5+1), 256) ||  /* back porch */
> >>>           CHECK(left_margin, (5+1), 256) ||   /* front porch */
> >>>           CHECK(hsync_len, (5+1), 256) ||
> >>>           var->xres > 4096 ||
> >>>
> >>> These 4 checks don't match the actual values that can be
> >>> generated by the CLCD controller. The minimum values for left
> >>> and right horizontal porch and HSYNC width can go down to
> >>> 1 clock.
> >>
> >> Not quite - these restrictions deal with the restrictions for DMA
> >> timing for STN panels as specified in the CLCD documentation -
> >> clcdfb_check doesn't deal with the differences between STN and
> >> active panels.
> >>
> >> So it's not as simple as just reducing these down to allowing 1 clock
> >> - that'd break STN panels.
> >>
> >
> > I didn't realize those limits were for STN. With TFT HS width at 5 clocks,
> > the check fails on my board, I'll have to create a variant of this function
> > on the phy3250 platform.
> >
> 
>        if (CHECK(right_margin, (5+1), 256) ||  /* back porch */
>            CHECK(left_margin, (5+1), 256) ||   /* front porch */
>            CHECK(hsync_len, (5+1), 256) ||
>            var->xres > 4096 ||
> 
> The hsync_len has a minimum value of (3+1) on the pl11x and TFT panels
> can go as low as 2 clocks on HSW and HBP.
> 
> For TFT panels, HBP and HSW can go as low as 2 clocks.
> 
> I think the limits should be fixed in clcd.h for STN and another variant added
> for TFT. Will this work?

We do have a flag which indicates what type of panel is connected - we
could use that to select the minimum requirements to test in this
function.