[PATCH 1/3 v2] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L=

[Santosh Shilimkar]

1 entries

This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED
types so that at boot-up, we can map memories outside system memory
at page level granularity

Previously the mapping was limiting to section level, which creates
unnecessary additional mapping for which physical memory may not
present. On the newer ARM with speculation, this is dangerous and can
result in untraceable aborts.

The patch is based on inputs from Russell King

Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
arch/arm/mm/mmu.c |   17 +++++++++++++++--
 1 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6..3e986a6 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -246,6 +246,9 @@ static struct mem_type mem_types[] =3D {
 		.domain    =3D DOMAIN_USER,
 	},
 	[MT_MEMORY] =3D {
+		.prot_pte  =3D L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+				L_PTE_USER | L_PTE_EXEC,
+		.prot_l1   =3D PMD_TYPE_TABLE,
 		.prot_sect =3D PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 		.domain    =3D DOMAIN_KERNEL,
 	},
@@ -254,6 +257,9 @@ static struct mem_type mem_types[] =3D {
 		.domain    =3D DOMAIN_KERNEL,
 	},
 	[MT_MEMORY_NONCACHED] =3D {
+		.prot_pte  =3D L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+				L_PTE_USER | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
+		.prot_l1   =3D PMD_TYPE_TABLE,
 		.prot_sect =3D PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 		.domain    =3D DOMAIN_KERNEL,
 	},
@@ -411,9 +417,12 @@ static void __init build_mem_type_table(void)
 	 * Enable CPU-specific coherency if supported.
 	 * (Only available on XSC3 at the moment.)
 	 */
-	if (arch_is_coherent() && cpu_is_xsc3())
+	if (arch_is_coherent() && cpu_is_xsc3()) {
 		mem_types[MT_MEMORY].prot_sect |=3D PMD_SECT_S;
-
+		mem_types[MT_MEMORY].prot_pte |=3D L_PTE_SHARED;
+		mem_types[MT_MEMORY_NONCACHED].prot_sect |=3D PMD_SECT_S;
+		mem_types[MT_MEMORY_NONCACHED].prot_pte |=3D L_PTE_SHARED;
+	}
 	/*
 	 * ARMv6 and above have extended page tables.
 	 */
@@ -438,7 +447,9 @@ static void __init build_mem_type_table(void)
 		mem_types[MT_DEVICE_CACHED].prot_sect |=3D PMD_SECT_S;
 		mem_types[MT_DEVICE_CACHED].prot_pte |=3D L_PTE_SHARED;
 		mem_types[MT_MEMORY].prot_sect |=3D PMD_SECT_S;
+		mem_types[MT_MEMORY].prot_pte |=3D L_PTE_SHARED;
 		mem_types[MT_MEMORY_NONCACHED].prot_sect |=3D PMD_SECT_S;
+		mem_types[MT_MEMORY_NONCACHED].prot_pte |=3D L_PTE_SHARED;
 #endif
 	}
=20
@@ -475,6 +486,8 @@ static void __init build_mem_type_table(void)
 	mem_types[MT_LOW_VECTORS].prot_l1 |=3D ecc_mask;
 	mem_types[MT_HIGH_VECTORS].prot_l1 |=3D ecc_mask;
 	mem_types[MT_MEMORY].prot_sect |=3D ecc_mask | cp->pmd;
+	mem_types[MT_MEMORY].prot_pte |=3D kern_pgprot;
+	mem_types[MT_MEMORY_NONCACHED].prot_sect |=3D ecc_mask;
 	mem_types[MT_ROM].prot_sect |=3D cp->pmd;
=20
 	switch (cp->pmd) {
--=20
1.6.0.4


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