Add support for the 16-way L310 L2 cache controller
Will Deacon
will.deacon at arm.com
Thu Apr 29 12:20:35 EDT 2010
Hi Jason,
The patch entitled `Add support for the 16-way L310 L2 cache controller'
which you submitted to RMK's patch system appears to perform a 16-way
invalidation even when the ways might not be present. This results in
writes to the reserved bits [15:8] of the invalidate-by-way ctrl register.
You can check the associativity by reading bit 16 of the auxiliary ctrl
register.
Will
More information about the linux-arm-kernel
mailing list