[PATCH v4 1/2] spi: implemented driver for Cirrus EP93xx SPI controller

[Martin Guy]

On 4/22/10, H Hartley Sweeten <hartleys at visionengravers.com> wrote:
>  First, every spi transaction, including a single byte transfer, is
>  going to generate at least two interrupts.  One when the interrupts
>  are first enabled because the TX FIFO is empty.  And a second when
>  that byte has been transferred and the TX FIFO is again empty.
>
>  The first interrupt can be prevented by priming the TX FIFO before
>  enabling the interrupts.  All you need to do is call ep93xx_spi_read_write
>  right before ep93xx_spi_enable_interrupts.

Nice. That increases the data throughput from 367 to 372 kB/sec and
reduces the CPU usage from 61 to 60.2% for large transfers

    M