[PATCH] arm: remove unused code in delay.S
Steve Chen
schen at mvista.com
Wed Sep 16 10:49:14 EDT 2009
On Wed, 2009-09-16 at 14:30 +0200, Krzysztof Halasa wrote:
> Steve Chen <schen at mvista.com> writes:
>
> > +config OLD_CPU_DELAY
> > + depends on CPU_32v3 || CPU_32v4 || CPU_32v4T
> > + bool "Accurate delays for some older CPUs"
> > + def_bool n
> > + help
> > + Try enable this if observing longer than expected delays and need
> > + more accuracy. May cause instability in some CPUs.
> > +
>
> There is still this uncertain "accurate" in the text. Why don't just
>
> + bool "Different delay() code for some older CPUs"
Sounds good. I also update text under help to better quantify
"accuracy". Updated patch below. Separately, as Russel pointed out,
this should only be done by experienced people, so we even bother with
this patch since the only people should touch this are the people who
knows all the details.
Document #if 0 code block in delay.S and make it selectable for compile.
Signed-off-by: Steve Chen <schen at mvista.com>
---
arch/arm/Kconfig | 8 ++++++++
arch/arm/lib/delay.S | 2 +-
2 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aef63c8..ca8d535 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -813,6 +813,14 @@ config ARM_ERRATA_460075
ACTLR register. Note that setting specific bits in the ACTLR
register
may not be available in non-secure mode.
+config OLD_CPU_DELAY
+ depends on CPU_32v3 || CPU_32v4 || CPU_32v4T
+ bool "Different delay() code for some older CPUs"
+ def_bool n
+ help
+ Try enable this if observing longer than expected delays. This code
+ improves accuracy for some CPUs while cause instability in others.
+
endmenu
source "arch/arm/common/Kconfig"
diff --git a/arch/arm/lib/delay.S b/arch/arm/lib/delay.S
index 8d6a876..67e679b 100644
--- a/arch/arm/lib/delay.S
+++ b/arch/arm/lib/delay.S
@@ -42,7 +42,7 @@ ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06
@ Delay routine
ENTRY(__delay)
subs r0, r0, #1
-#if 0
+#ifdef CONFIG_OLD_CPU_DELAY
movls pc, lr
subs r0, r0, #1
movls pc, lr
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