LDREX/STREX and pre-emption on *non*-SMP hardware

Jamie Lokier jamie at shareable.org
Sun Sep 13 21:44:04 EDT 2009

Catalin Marinas wrote:
> > But what about a single CPU system?
> With two or more threads, you can have something like below, even on UP
> systems:
> T1			T2
> 			LDREX
>  			STREX (succeeds)
> 			LDREX
> STREX (succeeds)
> 			STREX (fails)
> Thread T2 perform two successive atomic modifications but the context
> switch happens during the second one, so STREX in T1 should not succeed.

That's very convincing, and you are right of course.  Thanks!

-- Jamie

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