[PATCH v2 RESEND 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size
sshtylyov at ru.mvista.com
Sat Sep 12 10:21:01 EDT 2009
Kirill A. Shutemov wrote:
>>> Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
>>> It's not true at least for CPUs based on Cortex-A8.
>>> List of CPUs with cache line size != 32 should be expanded later.
>>> Signed-off-by: Kirill A. Shutemov <kirill at shutemov.name>
>>> arch/arm/include/asm/cache.h | 2 +-
>>> arch/arm/mm/Kconfig | 5 +++++
>>> 2 files changed, 6 insertions(+), 1 deletions(-)
>>> diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
>>> index feaa75f..2ee7743 100644
>>> --- a/arch/arm/include/asm/cache.h
>>> +++ b/arch/arm/include/asm/cache.h
>>> @@ -4,7 +4,7 @@
>>> #ifndef __ASMARM_CACHE_H
>>> #define __ASMARM_CACHE_H
>>> -#define L1_CACHE_SHIFT 5
>>> +#define L1_CACHE_SHIFT (CONFIG_ARM_L1_CACHE_SHIFT)
>> Parens not needed.
> You can write anything in your .config (like 2+3), so I think parens is needed.
You can -- but that won't be an integer option.
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