[PATCH] Use Normal uncached memory rather than Strongly Ordered on ARMv6+

[Catalin Marinas]

On Fri, 2009-10-23 at 13:36 +0100, Russell King - ARM Linux wrote:
> If you have a shared ownership ring buffer, you need the writes for
> updating the DMA pointers to hit it before the write to change the
> ownership of the descriptor to device.  Reverse those two writes and
> you end up transmitting junk.

But if we have arch_is_coherent() enabled (possibly with hardware
support like ARM's ACP), we need the drivers to have barriers anyway
since we would use normal cached memory (and ordering isn't guaranteed).
Of course, one has to go through the drivers used with a platform and
check them but we already have a precedent.

BTW, there are two other architectures (x86 and PowerPC) with a similar
restriction. Do they do anything about this in Linux?

PowerPC, 4.8.1 (page 36):

http://pcsostres.ac.upc.edu/cellsim/lib/exe/fetch.php/book_iii.powerpc_operating_environment_architecture.version_2.01.es-archpub3.pdf?id=additional_cell_documents&cache=cache

x86, 10.12.4 (page 10-44):

ftp://download.intel.com/support/processors/celeron/sb/25366820.pdf

-- 
Catalin