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/*
 * This is normally called from the decompressor code.  The requirements
 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
 * r1 = machine nr, r2 = atags pointer.
 */

Since D-cache is off when entering kernel then what's the point of flushing
data cache here? In theory we only need make sure the whole cache is
invalidated right? So that when MMU is enabled the cache is in a clean
status with everything new loaded.

I'm asking this is I'm running a simulation and somehow the simulation can
not continue when data cache is cleaned but invalidate only works. My doubt
is since the cache content is garbage when chip is powered on, "xxx" data
may be flushed to memory if "clean and invalidate" is performed, which cause
my simulation problem.

Any one can help me understand this? Thanks in advance.

-Tim

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Hi,<div>I have a question regarding the data cache flush routine called at =
the beginning of kernel start up. At the beginning of the start up code, af=
ter processor type and machine type look up and simple page table created, =
a __switch_data is called which goes to=A0__v7_setup in my case (since the =
CPU is A9). Then at the beginning of the function it calls v7_flush_dcache_=
all. This cache routine is in cache-v7.S and I see it actually does &quot;c=
lean and invalidate&quot; operation as opposed to invalidate only.</div>
<div><br></div><div>From Russell&#39;s comment I can see this is the kernel=
 start requirement:</div><div><div><br></div><div>/*</div><div>=A0* This is=
 normally called from the decompressor code. =A0The requirements</div><div>
=A0* are: MMU =3D off, D-cache =3D off, I-cache =3D dont care, r0 =3D 0,</d=
iv><div>=A0* r1 =3D machine nr, r2 =3D atags pointer.</div><div>=A0*/</div>=
<div><br></div><div>Since D-cache is off when entering kernel then what&#39=
;s the point of flushing data cache here? In theory we only need make sure =
the whole cache is invalidated right? So that when MMU is enabled the cache=
 is in a clean status with everything new loaded.</div>
<div><br></div><div>I&#39;m asking this is I&#39;m running a simulation and=
 somehow the simulation can not continue when data cache is cleaned but inv=
alidate only works. My doubt is since the cache content is garbage when chi=
p is powered on, &quot;xxx&quot; data may be flushed to memory if &quot;cle=
an and invalidate&quot; is performed, which cause my simulation problem.</d=
iv>
<div><br></div><div>Any one can help me understand this? Thanks in advance.=
</div><div><br></div><div>-Tim</div><div><br></div><div><br></div><div><br>=
</div><div><br></div></div><div><br></div>

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