[PATCH 3/6] pxa: fix pxa168 lcd controller vsync/hsync timing error

[Eric Miao]

On Tue, Nov 3, 2009 at 2:45 PM, Jun Nie <niej0001 at gmail.com> wrote:
> pxa: fix pxa168 lcd controller vsync/hsync timing error
>
> Signed-off-by: Jun Nie <njun at marvell.com>
> ---
>  drivers/video/pxa168fb.c |    4 ++--
>  include/video/pxa168fb.h |    2 --
>  2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/video/pxa168fb.c b/drivers/video/pxa168fb.c
> index 2ba1444..bdd524c 100644
> --- a/drivers/video/pxa168fb.c
> +++ b/drivers/video/pxa168fb.c
> @@ -459,8 +459,8 @@ static void set_dumb_panel_control(struct fb_info *info)
>        x |= mi->invert_composite_blank ? 0x00000040 : 0;
>        x |= (info->var.sync & FB_SYNC_COMP_HIGH_ACT) ? 0x00000020 : 0;
>        x |= mi->invert_pix_val_ena ? 0x00000010 : 0;
> -       x |= (info->var.sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x00000008;
> -       x |= (info->var.sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x00000004;
> +       x |= (info->var.sync & FB_SYNC_VERT_HIGH_ACT) ? 0x00000008 : 0;
> +       x |= (info->var.sync & FB_SYNC_HOR_HIGH_ACT) ? 0x00000004 : 0;

Hi Jun,

Could you please help double check this? My understanding is
FB_SYNC_VERT_HIGH_ACT means it's a positive pulse covering all the
valid HSYNCs, and a rising edge of VSYNC means a start of the frame.

However, CFG_INV_VSYNC is '1' means the opposite.