[patch 2/4] [ARM] mmp: support marvell ARMADA610

[Haojian Zhuang]

On Mon, Dec 28, 2009 at 10:49 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> Haojian,
>
> Several suggestions:
>
> 1. entry-macro.S, could we simplify (and improve the performance a bit) to
> something like (haven't tested yet - let me know the result):
>
>        .macro  get_irqnr_preamble, base, tmp
>        mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
>        mov     \tmp, \tmp, lsr #4
>        and     \tmp, \tmp, #0xfff

We shouldn't use #0xfff in and instruction. Immediate number shouldn't
beyond 8bit. We have to use ldr instruction or multiple instrunctions.

>        cmp     \tmp, #0x581                    @ MMP2
>        moveq   \base, #MMP2_ICU_PJ4_IRQ_SEL
>        movne   \base, #ICU_AP_IRQ_SEL_INT_NUM
>        .endm
>
>        .macro  arch_ret_to_user, tmp1, tmp2
>        .endm
>
>        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
>        ldr     \tmp, [\base, #0]
>        and     \irqnr, \tmp, #0x3f             @ Interrupt Number
>        tst     \tmp, #(1 << 6)                 @ Interrupt Pending ?
>        .endm
>

I don't like this way. Although more jump instructions are used in irq
entry, it can be extended easier for supporting more silicons.

I've updated these patches in attached mail.

Thanks
Haojian
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