shared memory problem on ARM v5TE using threads

[Pavel Machek]

On Fri 2009-12-18 19:16:26, Russell King - ARM Linux wrote:
> On Fri, Dec 18, 2009 at 07:45:19PM +0100, Pavel Machek wrote:
> > But that's pretty unusual situation, right?
> 
> It may be uncommon, but it's something that must work - not only is it
> a quality of implementation issue, but its also a data corruption issue.
> Get it wrong and you silently corrupt files on your filesystems.
> 
> As I've said earlier in the thread, we know that db4 does this.  Not
> fixing this means that we really don't care about any program which
> uses db4, or data contained within a db4 database.

I'm not trying to argue it does not need to be fixed; I'm trying to
say that performance penalty in unusual case may be ok.

> > So what about...
> > 
> > a) flush L2 on context switch
> 
> If you go to that extent, the system will probably perform better with
> the L2 cache permanently disabled.

Are you sure? Context switches are not that common (3 times a second
in number-crunching cases?) and L2 cache should help performance quite
a lot. 

> > b) disable L2 when thread has maps one physical address twice
> 
> Due to the way the L2 cache works, you have to disable L2 and flush it
> when switching to the thread, and re-enable L2 when you switch away.
> Merely flushing it when switching away won't work.
> 
> In order to disable or enable the L2 cache, the L1 cache must be
> flushed and disabled - and that would have to be done with all IRQs
> (including FIQs) disabled to ensure that its done atomically.
> 
> I don't think this is a sane option.

Well, it sounds slow and it will not be easy to implement. It really
depends how much L2 cache helps on those systems. (I'd guess PC with
L2 disabled would run at half a speed. If performance penalty for L2
disabled is similar on those systems, extra complexity may be worth
it.)

So I guess someone with affected system needs to do some benchmarking.
									Pavel
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