shared memory problem on ARM v5TE using threads

[Nicolas Pitre]

On Wed, 16 Dec 2009, christian pellegrin wrote:

> On Wed, Dec 16, 2009 at 5:35 PM, christian pellegrin <chripell at gmail.com> wrote:
> 
> >
> > I'm trying some more elaborate tests where just one case of
> > inconsistency will stop the counting.
> >
> 
> Here is the program that implements Russell's ideas (at least I think
> so) but is easier to use. By giving the parameter 1 or -1 you can test
> different kind of consistency issues (missing flush in r/w or
> inconsistent mapping's cacheness). It is also quite fun to watch at
> with the buggy kernel on an idle system: it looks like that every
> couple of seconds the 256kb L2 cache get flushed anyway (so even on
> the kernel without the patch every now and then you get some
> progress). I had it running for tens of minutes on a patched kernel
> without stops.

Could you please repost your patch, adding CONFIG_CPU_CACHE_VIVT to the 
conditional code flushing the L2 cache in flush_dcache_page()?

I think this would be a good thing to have merged.  If I'm not mistaken, 
this patch appears to fix all identified coherency cases so far.


Nicolas