shared memory problem on ARM v5TE using threads

Ronen Shitrit rshitrit at marvell.com
Wed Dec 16 09:08:32 EST 2009



-----Original Message-----
From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-kernel-bounces at lists.infradead.org] On Behalf Of Russell King - ARM Linux
Sent: Tuesday, December 15, 2009 7:19 PM
To: christian pellegrin
Cc: linux-arm-kernel at lists.infradead.org
Subject: Re: shared memory problem on ARM v5TE using threads

On Tue, Dec 15, 2009 at 04:31:35PM +0100, christian pellegrin wrote:
> The patch here does what was described by Russell and seems to solve
> the read/write and the MAP_PRIVATE in test cases like the one I
> posted. As noted it may not be enough.

This might be enough (but needs thorough testing).  However, adding
the requirement for L2 cache flushing in flush_dcache_page() because
you have an L2 cache is unfair on those L2's which don't suffer from
this problem.

I think we need to have a little more information about the behaviour
of the L2 cache so that we can decide how much flushing is required,
and where.
[Ronen Shitrit] What information do you need?


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