shared memory problem on ARM v5TE using threads

[saeed bishara]

> I ran it on an ARM926EJ-S, which is ARMv5 and worked fine.
>
does it have L2 cache?
> If there's no problem with C=0 B=1 mappings on Kirkwood, I've no idea
> what's going on, and I don't have any suggestion on what to try next.
>
> The log shows that the kernel is doing the right thing: when we detect
> two mappings for the same page in the same MM space, we clean and
> invalidate any existing cacheable mappings visible in the MM space
> (both L1 and L2), and switch all visible mappings to C=0 B=1 mappings.
> This makes the area non-cacheable.
what about the PTE of the MM space of the write process? if it remains
C=1 B=1, then it's data will be at the L2, and as the L2 is not
flushed on context switch, then that explains this behavior.