[PATCH 2/2] dt-bindings: usb: snps,dwc3: Fix downstream port numbering

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] dt-bindings: usb: snps,dwc3: ABI breakage and semantic mismatch for OF graph ports
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commit 8b21cb9c9f29433cb69a312829ee4e457fe73ca5
Author: Chen-Yu Tsai <wenst at chromium.org>

dt-bindings: usb: snps,dwc3: Fix downstream port numbering

The DWC3 controller can operate in host mode, and USB downstream ports start
from 1, not 0. This commit reconciles the downstream port numbering with the
common USB host binding by renumbering ports 0 and 1 to 1 and 2, which is
explicitly noted as non-backwards compatible.

> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> index 6c0b8b6538246..4b6304bd2ec16 100644
> --- a/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
> @@ -410,11 +410,11 @@ properties:
>        property is used.
>  
>      properties:
> -      port at 0:
> +      port at 1:
>          $ref: /schemas/graph.yaml#/properties/port
>          description: High Speed (HS) data bus.
>  
> -      port at 1:
> +      port at 2:
>          $ref: /schemas/graph.yaml#/properties/port
>          description: Super Speed (SS) data bus.

[Severity: High]
Does this change break ABI backwards compatibility for existing in-tree
device trees?

For example, existing in-tree device trees like
arch/arm64/boot/dts/qcom/sm6115.dtsi already define port at 0 for HS and
port at 1 for SS:

					port at 0 {
						reg = <0>;

						usb_dwc3_hs: endpoint {
						};
					};

					port at 1 {
						reg = <1>;

						usb_dwc3_ss: endpoint {
							remote-endpoint = <&usb_qmpphy_usb_ss_in>;
						};
					};

These existing device trees will now fail dtbs_check schema validation
because port at 0 is no longer valid, and port at 1 is documented as High Speed
when existing trees use it for Super Speed.

Furthermore, when the WIP OF graph host mode connections mentioned in the
commit message are merged, will a future kernel attempting to configure
port at 1 as the High Speed port functionally break USB host mode on older
DTBs that route port at 1 to the Super Speed PHY?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261014082037.1774672-1-wenst@chromium.org?part=2