[PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL clock controller

[Jian Hu via B4 Relay]

From: Jian Hu <jian.hu at amlogic.com>

Add the PLL clock controller dt-bindings for the Amlogic A9 SoC family.

Signed-off-by: Jian Hu <jian.hu at amlogic.com>
---
 .../bindings/clock/amlogic,a9-pll-clkc.yaml        | 110 +++++++++++++++++++++
 include/dt-bindings/clock/amlogic,a9-pll-clkc.h    |  55 +++++++++++
 2 files changed, 165 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml
new file mode 100644
index 000000000000..4ee6013ba1a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2026 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,a9-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic A9 Series PLL Clock Controller
+
+maintainers:
+  - Neil Armstrong <neil.armstrong at linaro.org>
+  - Jerome Brunet <jbrunet at baylibre.com>
+  - Jian Hu <jian.hu at amlogic.com>
+  - Xianwei Zhao <xianwei.zhao at amlogic.com>
+
+properties:
+  compatible:
+    enum:
+      - amlogic,a9-gp0-pll
+      - amlogic,a9-hifi0-pll
+      - amlogic,a9-hifi1-pll
+      - amlogic,a9-mclk0-pll
+      - amlogic,a9-mclk1-pll
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    items:
+      - description: pll input oscillator gate
+      - description: fixed input clock source for mclk_sel_0
+      - description: u3p2pll input clock source for mclk_sel_0 (optional)
+    minItems: 1
+
+  clock-names:
+    items:
+      - const: in0
+      - const: in1
+      - const: in2
+    minItems: 1
+
+required:
+  - compatible
+  - '#clock-cells'
+  - reg
+  - clocks
+  - clock-names
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - amlogic,a9-mclk0-pll
+              - amlogic,a9-mclk1-pll
+
+    then:
+      properties:
+        clocks:
+          maxItems: 3
+
+        clock-names:
+          maxItems: 3
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - amlogic,a9-gp0-pll
+              - amlogic,a9-hifi0-pll
+              - amlogic,a9-hifi1-pll
+
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+
+        clock-names:
+          maxItems: 1
+
+additionalProperties: false
+
+examples:
+  - |
+    apb4 {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        clock-controller at 8200 {
+            compatible = "amlogic,a9-gp0-pll";
+            reg = <0x0 0x8200 0x0 0x20>;
+            #clock-cells = <1>;
+            clocks = <&scmi_clk 0>;
+            clock-names = "in0";
+        };
+
+        clock-controller at 8330 {
+            compatible = "amlogic,a9-mclk0-pll";
+            reg = <0x0 0x8330 0x0 0x14>;
+            #clock-cells = <1>;
+            clocks = <&scmi_clk 4>,
+                     <&scmi_clk 8>;
+            clock-names = "in0", "in1";
+        };
+    };
diff --git a/include/dt-bindings/clock/amlogic,a9-pll-clkc.h b/include/dt-bindings/clock/amlogic,a9-pll-clkc.h
new file mode 100644
index 000000000000..31edb0bc95e7
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a9-pll-clkc.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AMLOGIC_A9_PLL_CLKC_H
+#define __AMLOGIC_A9_PLL_CLKC_H
+
+/* GP0 */
+#define CLKID_GP0_IN_DIV2_DIV		0
+#define CLKID_GP0_IN_DIV2		1
+#define CLKID_GP0_PLL_DCO		2
+#define CLKID_GP0_PLL			3
+
+/* HIFI0 */
+#define CLKID_HIFI0_IN_DIV2_DIV		0
+#define CLKID_HIFI0_IN_DIV2		1
+#define CLKID_HIFI0_PLL_DCO		2
+#define CLKID_HIFI0_PLL			3
+
+/* HIFI1 */
+#define CLKID_HIFI1_IN_DIV2_DIV		0
+#define CLKID_HIFI1_IN_DIV2		1
+#define CLKID_HIFI1_PLL_DCO		2
+#define CLKID_HIFI1_PLL			3
+
+/* MCLK0 */
+#define CLKID_MCLK0_IN_DIV2		0
+#define CLKID_MCLK0_PLL_DCO		1
+#define CLKID_MCLK0_0_PLL		2
+#define CLKID_MCLK0_0_PRE		3
+#define CLKID_MCLK0_0_SEL		4
+#define CLKID_MCLK0_0_DIV		5
+#define CLKID_MCLK0_0			6
+#define CLKID_MCLK0_1_PLL		7
+#define CLKID_MCLK0_1_PRE		8
+#define CLKID_MCLK0_1_SEL		9
+#define CLKID_MCLK0_1_DIV		10
+#define CLKID_MCLK0_1			11
+
+/* MCLK1 */
+#define CLKID_MCLK1_IN_DIV2		0
+#define CLKID_MCLK1_PLL_DCO		1
+#define CLKID_MCLK1_0_PLL		2
+#define CLKID_MCLK1_0_PRE		3
+#define CLKID_MCLK1_0_SEL		4
+#define CLKID_MCLK1_0_DIV		5
+#define CLKID_MCLK1_0			6
+#define CLKID_MCLK1_1_PLL		7
+#define CLKID_MCLK1_1_PRE		8
+#define CLKID_MCLK1_1_SEL		9
+#define CLKID_MCLK1_1_DIV		10
+#define CLKID_MCLK1_1			11
+
+#endif  /* __AMLOGIC_A9_PLL_CLKC_H */

-- 
2.47.1