[PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu at amlogic.com>

Add the SCMI clock controller dt-bindings for Amlogic A4 SoC family.

Signed-off-by: Chuan Liu <chuan.liu at amlogic.com>
---
 include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 ++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/include/dt-bindings/clock/amlogic,a4-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a4-scmi-clkc.h
new file mode 100644
index 000000000000..454e492f8f6f
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a4-scmi-clkc.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2025 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu at amlogic.com>
+ */
+
+#ifndef __AMLOGIC_A4_SCMI_CLKC_H
+#define __AMLOGIC_A4_SCMI_CLKC_H
+
+#define CLKID_OSC				0
+#define CLKID_SYS_CLK				1
+#define CLKID_AXI_CLK				2
+#define CLKID_CPU_CLK				3
+#define CLKID_FIXED_PLL				4
+#define CLKID_GP1_PLL				5
+#define CLKID_ACLKM				6
+#define CLKID_SYS_PLL_DIV16			7
+#define CLKID_CPU_CLK_DIV16			8
+#define CLKID_FCLK_50M_PREDIV			9
+#define CLKID_FCLK_50M_DIV			10
+#define CLKID_FCLK_50M				11
+#define CLKID_FCLK_DIV2_DIV			12
+#define CLKID_FCLK_DIV2				13
+#define CLKID_FCLK_DIV2P5_DIV			14
+#define CLKID_FCLK_DIV2P5			15
+#define CLKID_FCLK_DIV3_DIV			16
+#define CLKID_FCLK_DIV3				17
+#define CLKID_FCLK_DIV4_DIV			18
+#define CLKID_FCLK_DIV4				19
+#define CLKID_FCLK_DIV5_DIV			20
+#define CLKID_FCLK_DIV5				21
+#define CLKID_FCLK_DIV7_DIV			22
+#define CLKID_FCLK_DIV7				23
+#define CLKID_SYS_MMC_PCLK			24
+#define CLKID_SYS_CPU_CTRL			25
+#define CLKID_SYS_IRQ_CTRL			26
+#define CLKID_SYS_GIC				27
+#define CLKID_SYS_BIG_NIC			28
+#define CLKID_AXI_SYS_NIC			29
+#define CLKID_AXI_CPU_DMC			30
+
+#endif /* __AMLOGIC_A4_SCMI_CLKC_H */

-- 
2.42.0