[PATCH] clk: meson-g12a: fix bit range for fixed sys and hifi pll

[Da Xue]

On Thu, Aug 21, 2025 at 4:43 PM Martin Blumenstingl
<martin.blumenstingl at googlemail.com> wrote:
>
> On Thu, Aug 14, 2025 at 10:09 PM Da Xue <da at libre.computer> wrote:
> >
> > The bit range 17:0 does not match the datasheet for A311D / S905D3.
> > Change the bit range to 19:0 for FIX and HIFI PLLs to match datasheet.
> I have:
> -  S905X3_Public_Datasheet_Hardkernel.pdf
> -  S922X_Datasheet_Wesion.pdf
> -  A311D_Datasheet_01_Wesion.pdf
> These state (for all three PLLs) that .frac is [18:0] (that's shift =
> 0 and width = 19).
> I get where you're coming from with 19:0 - in the context of this
> patch this can be misleading as it would mean that the fractional
> divider is 20 bits wide.

Yes, I was in a rush and missed this. The description is bad and I'll
spin a v2 with the Fixes as well as report the clock differences.

>
> > There's no frac for sys pll so add that as well.
> I first read this as sys pll does not have a fractional divider.
> What do you think about: "The frac field for sys pll is missing so add
> that as well"

Will correct in V2.

>
> I guess at this point this should include:
> Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
> > Signed-off-by: Da Xue <da at libre.computer>

Ack
>
> [...]
> Have you compared /sys/kernel/debug/meson-clk-msr/measure_summary and
> /sys/kernel/debug/clk/clk_summary before/after this patch?
> I'll test this during the weekend and then give my Tested/Reviewed by

Will provide in V2.

>
>
> Best regards,
> Martin