[PATCH 1/3] spi: dt-bindings: add doc for Amlogic A113L2 SFC

[Xianwei Zhao]

Hi Krzysztof,
    Thanks for your reply.

On 2025/8/17 15:20, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
> 
> On 14/08/2025 08:38, Xianwei Zhao wrote:
>> Hi Krzysztof,
>>      Thanks for your reply.
>>
>> On 2025/8/14 00:19, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On 13/08/2025 11:34, Xianwei Zhao wrote:
>>>> Hi Krzysztof,
>>>>       Thanks  for your reply.
>>>>
>>>> On 2025/8/13 15:36, Krzysztof Kozlowski wrote:
>>>>> [ EXTERNAL EMAIL ]
>>>>>
>>>>> On 13/08/2025 08:13, Xianwei Zhao wrote:
>>>>>>>> +allOf:
>>>>>>>> +  - $ref: /schemas/spi/spi-controller.yaml#
>>>>>>>> +
>>>>>>>> +properties:
>>>>>>>> +  compatible:
>>>>>>>> +    const: amlogic,a4-spifc
>>>>>>>> +
>>>>>>>> +  reg:
>>>>>>>> +    items:
>>>>>>>> +      - description: core registers
>>>>>>>> +      - description: parent clk control registers
>>>>>>>
>>>>>>> Why are you poking to parent node or to clock registers? This looks like
>>>>>>> mixing up device address spaces.
>>>>>>>
>>>>>>
>>>>>> The SPIFC bus clock multiplexes EMMC modules, so the corresponding
>>>>>> frequency division register is also in EMMC module. The SPIFC and the
>>>>>> EMMC modules cannot be used simultaneously.
>>>>>
>>>>> Then obviously you cannot put here EMMC or parent registers.
>>>>>
>>>>> It looks really like you miss proper hardware representation.
>>>>>
>>>>
>>>> It does seem a bit unusual. However, in our hardware design, EMMC and
>>>> SFC modules are integrated, and they share common resources such as the
>>>> clock and I/O pins .They are mutually exclusive.
>>>>
>>>
>>> How did you express it in DT? This looks similar to serial engines and
>>> such are not implemented independently.
>>>
>>
>> The hardware design provides this clock for both modules — EMMC and
>> SPIFC. A control bit (bit 31: Cfg_NAND, where 0 = Port C only, 1 = NAND)
>> is used to determine which module uses the clock.
>>
>> It's not that NAND is using EMMC’s resources; rather, the configuration
>> register controlling this selection is located within the EMMC module,
>> which makes the setup appear somewhat unusual.
> 
> No, how did you express in DT that they are mutually exclusive?
> 

I will remove this part of the register description. The clock 
implementation will be placed in the common module. The SFC is only used 
as a consumer for the clock.

>>
>> In the device tree (DT), I'll just refer directly to the clock frequency
>> division control register.
> 
> This does not solve the exclusive usage...
> 
> 
> Best regards,
> Krzysztof