[PATCH v2] drm/meson: disable line encoder before programming the gamma table

[Theo Debrouwere]

There is a very rare bug, where the gamma table can't be written correctly.
It is possible to write some entries into the gamma data port, after which
the WR_RDY bit isn't set anymore. This causes a timeout in the code, and more
entries will be written into the table. (each having their own timeout)
There will be an image produced, but the colors will be completely off.
The number of entries that can be written seems random.

The issue seems to be solved if the line encoder is disabled before the table
is programmed.

Fixes: 42dcf15f901c ("drm/meson: add DSI encoder")
Signed-off-by: Theo Debrouwere <theo.debrouwere at faytech.de>
---
Added Fixes tag.

 drivers/gpu/drm/meson/meson_encoder_dsi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.c b/drivers/gpu/drm/meson/meson_encoder_dsi.c
index 7816902f59075..15fd9df58ae4e 100644
--- a/drivers/gpu/drm/meson/meson_encoder_dsi.c
+++ b/drivers/gpu/drm/meson/meson_encoder_dsi.c
@@ -66,10 +66,11 @@ static void meson_encoder_dsi_atomic_enable(struct drm_bridge *bridge,
 	/* ENCL clock setup is handled by CCF */

 	meson_venc_mipi_dsi_mode_set(priv, &crtc_state->adjusted_mode);
-	meson_encl_load_gamma(priv);

 	writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));

+	meson_encl_load_gamma(priv);
+
 	writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, ENCL_VIDEO_MODE_ADV_VFIFO_EN,
 			    priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
 	writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
--
2.45.2