[PATCH v1 6/6] clk: meson: a1: add Amlogic A1 CPU clock controller driver

[Martin Blumenstingl]

Hi Dmitry,

On Fri, Mar 29, 2024 at 9:59 PM Dmitry Rokosov
<ddrokosov at salutedevices.com> wrote:
[...]
> +static struct clk_regmap cpu_fclk = {
> +       .data = &(struct clk_regmap_mux_data) {
> +               .offset = CPUCTRL_CLK_CTRL0,
> +               .mask = 0x1,
> +               .shift = 10,
> +       },
> +       .hw.init = &(struct clk_init_data) {
> +               .name = "cpu_fclk",
> +               .ops = &clk_regmap_mux_ops,
> +               .parent_hws = (const struct clk_hw *[]) {
> +                       &cpu_fsel0.hw,
> +                       &cpu_fsel1.hw,
Have you considered the CLK_SET_RATE_GATE flag for &cpu_fsel0.hw and
&cpu_fsel1.hw and then dropping the clock notifier below?
We use that approach with the Mali GPU clock on other SoCs, see for
example commit 8daeaea99caa ("clk: meson: meson8b: make the CCF use
the glitch-free mali mux").
It may differ from what Amlogic does in their BSP, but I don't think
that there's any harm (if it works in general) because CCF (common
clock framework) will set all clocks in the "inactive" tree and then
as a last step just change the mux (&cpu_fclk.hw). So at no point in
time will we get any other rate than a) the original CPU clock rate
before the rate change b) the new desired CPU clock rate. This is
because we have two symmetric clock trees.


Best regards,
Martin