[PATCH v3 0/7] clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver
Dmitry Rokosov
ddrokosov at salutedevices.com
Mon Jun 10 04:21:02 PDT 2024
On Mon, Jun 10, 2024 at 12:13:41PM +0200, Jerome Brunet wrote:
> On Wed 15 May 2024 at 21:47, Dmitry Rokosov <ddrokosov at salutedevices.com> wrote:
>
> > The CPU clock controller plays a general role in the Amlogic A1 SoC
> > family by generating CPU clocks. As an APB slave module, it offers the
> > capability to inherit the CPU clock from two sources: the internal fixed
> > clock known as 'cpu fixed clock' and the external input provided by the
> > A1 PLL clock controller, referred to as 'syspll'.
> >
> > It is important for the driver to handle the cpu_clk rate switching
> > effectively by transitioning to the CPU fixed clock to avoid any
> > potential execution freezes.
> >
>
> Please group your changes, fixes then bindings then driver.
Sure, thank you for the suggestion!
--
Thank you,
Dmitry
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