[PATCH] clk: meson: s4: fix fixed_pll_dco clock
Xianwei Zhao via B4 Relay
devnull+xianwei.zhao.amlogic.com at kernel.org
Mon Jun 3 03:04:33 PDT 2024
From: Xianwei Zhao <xianwei.zhao at amlogic.com>
The fixed_pll_dco output frequency is not accurate,
add frac factor for fixed_pll_dco clk to fix it.
Fixes: 57b55c76aaf1 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller")
Signed-off-by: Xianwei Zhao <xianwei.zhao at amlogic.com>
---
drivers/clk/meson/s4-pll.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c
index 8dfaeccaadc2..47c0c105e32d 100644
--- a/drivers/clk/meson/s4-pll.c
+++ b/drivers/clk/meson/s4-pll.c
@@ -38,6 +38,11 @@ static struct clk_regmap s4_fixed_pll_dco = {
.shift = 0,
.width = 8,
},
+ .frac = {
+ .reg_off = ANACTRL_FIXPLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
.n = {
.reg_off = ANACTRL_FIXPLL_CTRL0,
.shift = 10,
---
base-commit: ba535bce57e71463a86f8b33a0ea88c26e3a6418
change-id: 20240603-s4_fixedpll-392bb62ec978
Best regards,
--
Xianwei Zhao <xianwei.zhao at amlogic.com>
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