[PATCH v8 0/5] Add C3 SoC PLLs and Peripheral clock
Xianwei Zhao
xianwei.zhao at amlogic.com
Mon Apr 29 23:44:33 PDT 2024
Changes since V7 [1]:
- Remove included head file not used.
- Link to v7: https://lore.kernel.org/all/20240424050928.1997820-1-xianwei.zhao@amlogic.com
Changes since V6 [12]:
- Add pad src for rtc clock.
- Add SCMI clock controller support, move some clock node in SCMI,such as GP1 PLL DDR USB etc.
- Fix some spelling mistake.
- Use lower case for bindings and update some input clocks desc.
- Update some clock comments.
- Delete prefix "AML_" for macro definition.
- Addd some clock annotation and some clock flag CRITICAL.
- Add maximum for regmap_config.
- Delete some unused register definition and unused clock inputs.
- Drop patch subject redundant "bindings". Suggested by Krzysztof.
- Not reference header file "clk.h" and replace comment. Suggested by Jerome.
- Modify description about board in Kconfig file help item. Suggested by Jerome.
- Link to v6: https://lore.kernel.org/all/20231106085554.3237511-1-xianwei.zhao@amlogic.com
Changes since V5 [3]:
- Fix some typo and modify formart for MARCO. Suggested by Jerome.
- Add pad clock for peripheral input clock in bindings.
- Add some description for explaining why ddr_dpll_pt_clk and cts_msr_clk are out of tree.
Changes since V4 [10]:
- Change some fw_name of clocks. Suggested by Jerome.
- Delete minItem of clocks.
- Add CLk_GET_RATE_NOCACHE flags for gp1_pll
- Fix some format. and fix width as 8 for mclk_pll_dco.
- exchange gate and divder for fclk_50m clock.
- add CLK_SET_RATE_PARENT for axi_a_divder & axi_b_divder.
- add CLK_IS_CRITICAL for axi_clk
- Optimized macro define for pwm clk.
- add cts_oscin_clk mux between 24M and 32k
- add some missing gate clock, such as ddr_pll.
Changes since V3 [7]:
- Modify Kconfig desc and PLL yaml clk desc.
- Fix some format.Suggested by Yixun and Jerome.
- Add flag CLK_GET_RATE_NOCACHE for sys_clk.
- Optimized macro define for pwm clk.
- Use flag CLK_IS_CRITICAL for axi_clk.
- Add some description for some clocks.
- Use FCLK_50M instead of FCLK_DIV40.
Changes since V2 [4]:
- Modify some format, include clk name & inline, and so on.
- Define marco for pwm clock.
- Add GP1_PLL clock.
- Modify yaml use raw instead of macro.
Changes since V1 [2]:
- Fix errors when check binding by using "make dt_binding_check".
- Delete macro definition.
Xianwei Zhao (5):
dt-bindings: clock: add Amlogic C3 PLL clock controller
dt-bindings: clock: add Amlogic C3 SCMI clock controller support
dt-bindings: clock: add Amlogic C3 peripherals clock controller
clk: meson: c3: add support for the C3 SoC PLL clock
clk: meson: c3: add c3 clock peripherals controller driver
.../clock/amlogic,c3-peripherals-clkc.yaml | 120 +
.../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +
drivers/clk/meson/Kconfig | 29 +
drivers/clk/meson/Makefile | 2 +
drivers/clk/meson/c3-peripherals.c | 2365 +++++++++++++++++
drivers/clk/meson/c3-pll.c | 746 ++++++
.../clock/amlogic,c3-peripherals-clkc.h | 212 ++
.../dt-bindings/clock/amlogic,c3-pll-clkc.h | 40 +
.../dt-bindings/clock/amlogic,c3-scmi-clkc.h | 27 +
9 files changed, 3600 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-peripherals-clkc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
create mode 100644 drivers/clk/meson/c3-peripherals.c
create mode 100644 drivers/clk/meson/c3-pll.c
create mode 100644 include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,c3-scmi-clkc.h
base-commit: ba535bce57e71463a86f8b33a0ea88c26e3a6418
--
2.39.2
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