[PATCH v1] meson saradc: fix clock divider mask length

[Dmitry Rokosov]

Hello Jonathan,

Thank you very much for the review!

On Sat, May 20, 2023 at 04:46:18PM +0100, Jonathan Cameron wrote:
> On Wed, 17 May 2023 16:47:59 +0000
> Старк Георгий Николаевич <GNStark at sberdevices.ru> wrote:
> 
> > On 5/16/23 22:08, Martin Blumenstingl wrote:
> > > Hi George,
> > >
> > > thank you for this patch!
> > >
> > > On Mon, May 15, 2023 at 11:06 PM George Stark <gnstark at sberdevices.ru> wrote:  
> > >> From: George Stark <GNStark at sberdevices.ru>
> > >>
> > >> According to datasheets of supported meson SOCs
> > >> length of ADC_CLK_DIV field is 6 bits long  
> > > I have a question about this sentence which doesn't affect this patch
> > > - it's only about managing expectations:
> > > Which SoC are you referring to?
> > > This divider is only relevant on older SoCs that predate GXBB (S905).
> > > To my knowledge all SoCs from GXBB onwards place the divider in the
> > > main or AO clock controller, so this bitmask is irrelevant there.  
> > 
> > Hello Martin
> > 
> > I've checked datasheets of all chips listed in meson_sar_adc_of_match array in meson_saradc.c and everywhere this field is 6 bits long. According to driver code and existing dts files this patch affects all supported chips except meson8.
> 
> On that note, do we want to add any clarifying text on the scope to the
> commit message?

To begin with, we will conduct all experiments that Martin mentioned in
another message within this thread. Once completed, we will share the
results in this current thread. If the changes are still relevant, we
will prepare a new patch set with a detailed commit message.

[...]

-- 
Thank you,
Dmitry