[PATCH v14 6/6] clk: meson: a1: add Amlogic A1 Peripherals clock controller driver

[Martin Blumenstingl]

Hi Dmitry,

overall this looks pretty good.

+Cc Heiner

On Wed, Apr 26, 2023 at 11:58 AM Dmitry Rokosov
<ddrokosov at sberdevices.ru> wrote:
[...]
> +static struct clk_regmap pwm_a_sel = {
> +       .data = &(struct clk_regmap_mux_data){
> +               .offset = PWM_CLK_AB_CTRL,
> +               .mask = 0x1,
> +               .shift = 9,
> +       },
> +       .hw.init = &(struct clk_init_data){
> +               .name = "pwm_a_sel",
> +               .ops = &clk_regmap_mux_ops,
> +               .parent_data = pwm_abcd_parents,
> +               .num_parents = ARRAY_SIZE(pwm_abcd_parents),
> +               /* For more information, please refer to rtc clock */
> +               .flags = CLK_SET_RATE_NO_REPARENT,
Heiner is working on a series that adds common clock support to the
PWM driver [0].
I think his plans for a next step are adding support for SoCs where
the PWM clocks are part of the peripheral clock controller (instead of
being part of the PWM controller registers).

Have you considered removing CLK_SET_RATE_PARENT from the &rtc clock
so downstream clocks won't change the rtc clock rate by accident?
Then we could drop the CLK_SET_RATE_NO_REPARENT flag from the PWM
clocks to allow them to pick the best available parent (whether that's
the rtc clock, xtal or sys_pll).
That said, it would require managing the CLKID_RTC_32K_SEL clock (or
it's parents) using assigned-clocks instead of doing so with the PWM
(and other) clocks. Whether this would cause problems: I'm not sure,
so I'm hoping that you can share some insights.


Best regards,
Martin


[0] https://lore.kernel.org/linux-amlogic/9faca2e6-b7a1-4748-7eb0-48f8064e323e@gmail.com/