Conflict between video-lut and pmu on meson-g12

[Martin Blumenstingl]

Hello Jiucheng Xu,

On Tue, Feb 28, 2023 at 10:04 PM Martin Blumenstingl
<martin.blumenstingl at googlemail.com> wrote:
[...]
> > A simple solution might be to specify the "actual" base of
> > the register set, and count from 0 in the driver?
> I think your fix is correct (formally it would need to be split into a
> driver and a .dtsi patch - but let's do things step by step).
While thinking more about this - I think the whole .dtsi code should
be improved. Both of the PMU IO regions are part of the &dmc region.
So I think &pmu should be moved inside &dmc (with the offsets adjusted
accordingly of course).

Also I think the dt-bindings are incomplete: according to the driver
code we're using XTAL as input clock.
But this is not described anywhere in the dt-bindings.
dt-bindings should always describe the hardware. The driver can decide
not to use it but the bindings must always be complete.
And with this comes the question: is the DMC PLL specific to the PMU
or is it shared with something else (e.g. the actual memory
controller)? On the 32-bit SoCs (Meson8b/S805 for example) there's a
whole DDR clock controller (used by the DDR memory controller), so I'm
wondering if these newer SoCs are still following that approach.


Best regards,
Martin