[PATCH v2 2/2] arm64: dts: amlogic: enable some nodes for board AQ222
Neil Armstrong
neil.armstrong at linaro.org
Fri Dec 8 04:14:59 PST 2023
On 08/12/2023 08:16, Xianwei Zhao via B4 Relay wrote:
> From: Xianwei Zhao <xianwei.zhao at amlogic.com>
>
> Add reserved memory for board AQ222 which is used by ATF.
> Enable NAND, SPICC nodes for board AQ222.
>
> Signed-off-by: Xianwei Zhao <xianwei.zhao at amlogic.com>
> ---
> .../boot/dts/amlogic/meson-s4-s805x2-aq222.dts | 56 ++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
> index c1f322c73982..18789242f05f 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
> @@ -23,6 +23,17 @@ memory at 0 {
> reg = <0x0 0x0 0x0 0x40000000>;
> };
>
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* 52 MiB reserved for ARM Trusted Firmware */
> + secmon_reserved: secmon at 5000000 {
> + reg = <0x0 0x05000000 0x0 0x3400000>;
> + no-map;
> + };
> + };
> };
>
> &uart_B {
> @@ -34,3 +45,48 @@ &ir {
> pinctrl-0 = <&remote_pins>;
> pinctrl-names = "default";
> };
> +
> +&nand {
> + status = "okay";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pinctrl-0 = <&nand_pins>;
> + pinctrl-names = "default";
> +
> + nand at 0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + nand-on-flash-bbt;
> +
> + partition at 0 {
> + label = "boot";
> + reg = <0x0 0x00200000>;
> + };
> + partition at 200000 {
> + label = "env";
> + reg = <0x00200000 0x00400000>;
> + };
> + partition at 600000 {
> + label = "system";
> + reg = <0x00600000 0x00a00000>;
> + };
> + partition at 1000000 {
> + label = "rootfs";
> + reg = <0x01000000 0x03000000>;
> + };
> + partition at 4000000 {
> + label = "media";
> + reg = <0x04000000 0x8000000>;
> + };
> + };
> +};
> +
> +&spicc0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spicc0_pins_x>;
> + cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>;
> +};
>
Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
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