[PATCH v4 4/4] pwm: meson: make full use of common clock framework

[Martin Blumenstingl]

On Wed, Apr 19, 2023 at 9:58 PM Heiner Kallweit <hkallweit1 at gmail.com> wrote:
[...]
> > This is a hack based on current clock values, either explicitly support a code path
> > where pre_div = 0 or if you can't do that with CCF implement the pinctrl way to handle this,
> > which is the cleanest.
> >
> To make it explicit we could request ULONG_MAX as rate instead of 1GHz, this would imply
> choosing mux parent with highest rate and pre_div = 0. Up to you whether this would be
> acceptable.
I like the idea of using ULONG_MAX as I first had to think about why
you chose 1GHz in the driver.

> AFAICS pinctrl would need quite some DTS changes, and it's not my area of expertise.
> So it would be open who can implement this.
My opinion is that this can be done in a separate patch. We need to
work on this whole thing anyways as you mentioned that newer SoCs
(from what I understand: G12A onwards) have a dedicated "constant
output" bit which will make the pinctrl solution unnecessary (at least
based on how I understand it).


Best regards,
Martin