[PATCH] spi: meson-spicc: save pow2 datarate between messages

[Mark Brown]

On Wed, Aug 10, 2022 at 11:17:14AM +0200, Neil Armstrong wrote:
> On 09/08/2022 17:27, Mark Brown wrote:
> > On Tue, Aug 09, 2022 at 05:20:19PM +0200, Neil Armstrong wrote:

> > When you say the value set by the clock framework does that mean that
> > the clock driver is adjusting hardware inside the SPI controller IP
> > block which is then getting reset by the SPI driver without the SPI
> > driver knowing about it?  That seems like a bad idea as you're finding
> > here.

> The SPI driver is explicitely triggering a reset at the end of each message
> to get back to a clean HW state, but it does reset the content of the "legacy"
> registers containing the power of 2 divider value, the new registers configuring
> the new clock divider path (only on newer SoCs) doesn't get cleared.

Sure, but that doesn't really address the concern - is this something
that the clk driver programmed or is this the driver forgetting to
restore a register that it programmed itself?  The commit message sounds
like the former which is a much bigger problem.
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