Amlogic Text Offset regression
Neil Armstrong
narmstrong at baylibre.com
Thu Nov 5 03:57:36 EST 2020
Hi,
On 05/11/2020 09:51, HK SH wrote:
> Hello,
>
> Since the text offset patch is removed from the kernel, no amlogic board is able to boot with 5.10-rc. While I can get it to boot only when I have mainline uboot and not all amlogic boards have mainline uboot support.
> I have tested Kernel 5.10-rc1 and 5.10.rc2 on Khadas VIm3 with mainline uboot and it works fine but when I try it on Odroid N2 or Odroid C4 then it gets stuck at starting kernel which seems that the kernel load address is not correct or something.
The only way to run Mainline Linux without the text offset patch/fix is to use the Legacy U-Boot image:
mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -n linux -d Image uImage
and use bootm
it's really a bug/regression in Amlogic's U-Boot fork, maybe HardKernel or Khadas could fix it.
Neil
> Odroid C4 Log below:
> SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:0;READ:0;0.0;CHK:0;
> bl2_stage_init 0x01
> bl2_stage_init 0x81
> hw id: 0x0000 - pwm id 0x01
> bl2_stage_init 0xc1
> bl2_stage_init 0x02
>
> L0:00000000
> L1:00000703
> L2:00008067
> L3:15000020
> S1:00000000
> B2:20282000
> B1:a0f83180
>
> TE: 119887
>
> BL2 Built : 20:29:41, Jun 18 2019. g12a ga659aac - luan.yuan at droid15-sz
>
> Board ID = 1
> Set cpu clk to 24M
> Set clk81 to 24M
> Use GP1_pll as DSU clk.
> DSU clk: 1200 Mhz
> CPU clk: 1200 MHz
> Set clk81 to 166.6M
> eMMC boot @ 0
> sw8 s
> DDR driver_vesion: LPDDR4_PHY_V_0_1_15 build time: Jun 18 2019 20:29:37
> board id: 1
> Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
> fw parse done
> Load ddrfw from eMMC, src: 0x00030200, des: 0xfffd0000, size: 0x0000c000, part: 0
> Load ddrfw from eMMC, src: 0x0002c200, des: 0xfffd0000, size: 0x00004000, part: 0
> PIEI prepare done
> fastboot data load
> 00000000
> emmc switch 1 ok
> 00000000
> emmc switch 2 ok
> fastboot data verify
> verify result: 255
> Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
> DDR4 probe
> ddr clk to 1320MHz
> Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
> 00000000
> emmc switch 0 ok
>
> dmc_version 0001
> Check phy result
> INFO : End of initialization
> INFO : End of read enable training
> INFO : End of fine write leveling
> INFO : End of read dq deskew training
> INFO : End of MPR read delay center optimization
> INFO : End of Write leveling coarse delay
> INFO : End of write delay center optimization
> INFO : End of read delay center optimization
> INFO : End of max read latency training
> INFO : Training has run successfully!
> 1D training succeed
> Load ddrfw from eMMC, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0
> Check phy result
> INFO : End of initialization
> INFO : End of 2D read delay Voltage center optimization
> INFO : End of 2D write delay Voltage center optimization
> INFO : Training has run successfully!
>
> R0_RxClkDly_Margin==106 ps 9
> R0_TxDqDly_Margi==118 ps 10
>
>
> R1_RxClkDly_Margin==0 ps 0
> R1_TxDqDly_Margi==0 ps 0
>
> dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001
>
> soc_vref_reg_value 0x 0000004f 00000051 0000004f 0000004e 00000050 0000004e 0000004e 0000004d 0000004e 0000004f 0000004e 00000050 0000004f 0000004c 0000004e 0000004e 0000004e 0000004d 00000050 0000004f 0000004f 0000004d 0000004d 000001
> 2D training succeed
> aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_15 build time: Jun 18 2019 20:29:43
> auto size-- 65535DDR cs0 size: 2048MB
> DDR cs1 size: 2048MB
> DMC_DDR_CTRL: 00700024DDR size: 3928MB
> cs0 DataBus test pass
> cs1 DataBus test pass
> cs0 AddrBus test pass
> cs1 AddrBus test pass
>
> non-sec scramble use zero key
> ddr scramble enabled
>
> 100bdlr_step_size ps== 450
> result report
> boot times 0Enable ddr reg access
> 00000000
> emmc switch 3 ok
> Authentication key not yet programmed
> get rpmb counter error 0x00000007
> 00000000
> emmc switch 0 ok
> Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
> Load BL3X from eMMC, src: 0x0003c200, des: 0x0172c000, size: 0x0009c000, part: 0
> bl2z: ptr: 05129330, size: 00001e40
> 0.0;M3 CHK:0;cm4_sp_mode 0
> MVN_1=0x00000000
> MVN_2=0x00000000
> [Image: g12a_v1.1.3386-3b31431 2019-05-21 10:41:54 luan.yuan at droid15-sz]
> OPS=0x10
> ring efuse init
> 2b 0c 10 00 01 31 15 00 00 09 36 30 43 57 50 50
> [0.017354 Inits done]
> secure task start!
> high task start!
> low task start!
> run into bl31
> NOTICE: BL31: v1.3(release):4fc40b1
> NOTICE: BL31: Built : 15:57:33, May 22 2019
> NOTICE: BL31: G12A normal boot!
> NOTICE: BL31: BL33 decompress pass
> ERROR: Error initializing runtime service opteed_fast
>
>
> U-Boot 2015.01 (Apr 14 2020 - 01:55:53)
>
> DRAM: 3.5 GiB
> Relocation Offset is: d6eef000
> spi_post_bind(spifc): req_seq = 0
> register usb cfg[0][1] = 00000000d7f83b88
> MMC: aml_priv->desc_buf = 0x00000000d3edf7c0
> aml_priv->desc_buf = 0x00000000d3ee1b00
> SDIO Port C: 0, SDIO Port B: 1
> co-phase 0x2, tx-dly 0, clock 400000
> co-phase 0x2, tx-dly 0, clock 400000
> co-phase 0x2, tx-dly 0, clock 400000
> emmc/sd response timeout, cmd8, status=0x1ff2800
> emmc/sd response timeout, cmd55, status=0x1ff2800
> co-phase 0x2, tx-dly 0, clock 400000
> co-phase 0x2, tx-dly 0, clock 40000000
> aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x142000
> [mmc_startup] mmc refix success
> [mmc_init] mmc init success
> In: serial
> Out: serial
> Err: serial
> vpu: error: vpu: check dts: FDT_ERR_BADMAGIC, load default parameters
> vpu: driver version: v20190313
> vpu: detect chip type: 12
> vpu: clk_level default: 7(666667000Hz), max: 7(666667000Hz)
> vpu: clk_level = 7
> vpu: vpu_power_on
> vpu: set_vpu_clk
> vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
> vpu: set_vpu_clk finish
> vpu: vpu_module_init_config
> vpp: vpp_init
> vpp: g12a/b osd1 matrix rgb2yuv ..............
> vpp: g12a/b osd2 matrix rgb2yuv..............
> vpp: g12a/b osd3 matrix rgb2yuv..............
> cvbs: cpuid:0x2b
> cvbs_config_hdmipll_g12a
> cvbs_set_vid2_clk
> reading boot-logo.bmp.gz
> ** Unable to read file boot-logo.bmp.gz **
> reading boot-logo.bmp
> ** Unable to read file boot-logo.bmp **
> movi: not registered partition name, logo
> movi - Read/write command from/to SD/MMC for ODROID board
>
> Usage:
> movi <read|write> <partition|sector> <offset> <address> [<length>]
> - <read|write> the command to access the storage
> - <offset> the offset from the start of given partiton in lba
> - <address> the memory address to load/store from/to the storage device
> - [<length>] the size of the block to read/write in bytes
> - all parameters must be hexa-decimal only
>
> [OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
> [OSD]set initrd_high: 0x3d800000
> [OSD]fb_addr for logo: 0x3d800000
> [OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
> [OSD]fb_addr for logo: 0x3d800000
> [OSD]VPP_OFIFO_SIZE:0xfff01fff
> [CANVAS]canvas init
> [CANVAS]addr=0x3d800000 width=5760, height=2160
> cvbs: outputmode[1080p60hz] is invalid
> vpp: vpp_matrix_update: 2
> set hdmitx VIC = 16
> config HPLL = 5940000 frac_rate = 1
> HPLL: 0x3b3a04f7
> HPLL: 0x1b3a04f7
> HPLLv1: 0xdb3a04f7
> config HPLL done
> j = 6 vid_clk_div = 1
> hdmitx phy setting done
> hdmitx: set enc for VIC: 16
> enc_vpu_bridge_reset[1319]
> rx version is 1.4 or below div=10
> USB3.0 XHCI init start
> Net: dwmac.ff3f0000
> Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
> ## Attempting fetch boot.ini in mmc:0...
> reading boot.ini
> 729 bytes read in 3 ms (237.3 KiB/s)
> ## Executing script at 04000000
> reading /Image
> 33964544 bytes read in 1112 ms (29.1 MiB/s)
> reading /dtbs/amlogic/meson-sm1-odroid-c4.dtb
> 71789 bytes read in 19 ms (3.6 MiB/s)
> reading /initramfs-linux.uimg
> 8448788 bytes read in 277 ms (29.1 MiB/s)
> [rsvmem] get fdtaddr NULL!
> rsvmem - reserve memory
>
> Usage:
> rsvmem check - check reserved memory
> rsvmem dump - dump reserved memory
>
> rsvmem check failed
> ## Loading init Ramdisk from Legacy Image at 03080000 ...
> Image Name: Ramdisk Image
> Image Type: AArch64 Linux RAMDisk Image (uncompressed)
> Data Size: 8448724 Bytes = 8.1 MiB
> Load Address: 00000000
> Entry Point: 00000000
> Verifying Checksum ... OK
> active_slot is <NULL>
> Unknown command 'store' - try 'help'
> No dtbo patitions found
> load dtb from 0x1000000 ......
> ## Flattened Device Tree blob at 20000000
> Booting using the fdt blob at 0x20000000
> libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
> No valid dtbo image found
> libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
> [rsvmem] fdt get prop fail.
> Loading Ramdisk to 3cff1000, end 3d7ffad4 ... OK
> Loading Device Tree to 000000001ffeb000, end 000000001ffff86c ... OK
>
> Starting kernel ...
>
> uboot time: 5251814 us
>
>
> Kindly advice what is the plan forward in regards to run mainline kernel on amlogic boards which does not have mainline uboot
>
> Furkan Kardame,
> Manjaro ARM Team.
>
>
> _______________________________________________
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> linux-amlogic at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>
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