[PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node

[Neil Armstrong]

On 15/08/2020 20:22, Martin Blumenstingl wrote:
> All IO mapped SoC peripherals should be within the "soc" node. Move the
> L2 cache-controller there as well since it's the only one not following
> this pattern.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> ---
>  arch/arm/boot/dts/meson.dtsi | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> index eadb0832bcfc..7649dd1e0b9e 100644
> --- a/arch/arm/boot/dts/meson.dtsi
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -11,13 +11,6 @@ / {
>  	#size-cells = <1>;
>  	interrupt-parent = <&gic>;
>  
> -	L2: cache-controller at c4200000 {
> -		compatible = "arm,pl310-cache";
> -		reg = <0xc4200000 0x1000>;
> -		cache-unified;
> -		cache-level = <2>;
> -	};
> -
>  	soc {
>  		compatible = "simple-bus";
>  		#address-cells = <1>;
> @@ -172,6 +165,13 @@ timer_abcde: timer at 9940 {
>  			};
>  		};
>  
> +		L2: cache-controller at c4200000 {
> +			compatible = "arm,pl310-cache";
> +			reg = <0xc4200000 0x1000>;
> +			cache-unified;
> +			cache-level = <2>;
> +		};
> +
>  		periph: bus at c4300000 {
>  			compatible = "simple-bus";
>  			reg = <0xc4300000 0x10000>;
> 

Reviewed-by: Neil Armstrong <narmstrong at baylibre.com>