[PATCH 1/1] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate

Jerome Brunet jbrunet at baylibre.com
Mon Sep 23 01:38:56 PDT 2019


On Sat 21 Sep 2019 at 17:04, Martin Blumenstingl <martin.blumenstingl at googlemail.com> wrote:

> The meson-saradc driver manually sets the input clock for
> sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
> GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
> to sar_adc_clk_sel which will let the common clock framework select the
> best matching parent clock if we want that.
>
> This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk
> drivers, which both also specify CLK_SET_RATE_PARENT.
>
> Fixes: 33d0fcdfe0e870 ("clk: gxbb: add the SAR ADC clocks and expose them")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>

Looks good. I'll apply it once rc1 is tagged
Thanks



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