[RFC/RFT v2 12/14] arm64: dts: meson-g12a: enable DVFS on G12A boards

Neil Armstrong narmstrong at baylibre.com
Mon Jul 1 02:07:52 PDT 2019


On 28/06/2019 20:08, Kevin Hilman wrote:
> Neil Armstrong <narmstrong at baylibre.com> writes:
> 
>> Enable DVFS for the U200, SEI520 and X96-Max Amlogic G12A based board
>> by setting the clock, OPP and supply for each CPU cores.
>>
>> The CPU cluster power supply can achieve 0.73V to 1.01V using a PWM
>> output clocked at 800KHz with an inverse duty-cycle.
>>
>> DVFS has been tested by running the arm64 cpuburn at [1] and cycling
>> between all the possible cpufreq translations and checking the final
>> frequency using the clock-measurer, script at [2].
>>
>> [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S
>> [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f
>>
>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> 
> [...]
> 
>> @@ -297,6 +316,34 @@
>>  	status = "okay";
>>  };
>>  
>> +&cpu0 {
>> +	cpu-supply = <&vddcpu>;
>> +	operating-points-v2 = <&cpu_opp_table>;
>> +	clocks = <&clkc CLKID_CPU_CLK>;
>> +	clock-latency = <50000>;
>> +};
>> +
>> +&cpu1 {
>> +	cpu-supply = <&vddcpu>;
>> +	operating-points-v2 = <&cpu_opp_table>;
>> +	clocks = <&clkc CLKID_CPU_CLK>;
>> +	clock-latency = <50000>;
>> +};
>> +
>> +&cpu2 {
>> +	cpu-supply = <&vddcpu>;
>> +	operating-points-v2 = <&cpu_opp_table>;
>> +	clocks = <&clkc CLKID_CPU_CLK>;
>> +	clock-latency = <50000>;
>> +};
>> +
>> +&cpu3 {
>> +	cpu-supply = <&vddcpu>;
>> +	operating-points-v2 = <&cpu_opp_table>;
>> +	clocks = <&clkc CLKID_CPU_CLK>;
>> +	clock-latency = <50000>;
>> +};
> 
> Just curious where this max clock transtion (clock-latency) value came
> from.  Were you able to measure that somehow?

It was taken from vendor tree. Haven't got chance to measure it, I assume
it's a safe value for now.

> 
> Kevin
> 




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