[PATCH 3/3] spi: meson-axg: add a linear clock divider support
yixun.lan at amlogic.com
Thu May 3 19:07:12 PDT 2018
On 05/04/18 07:16, Mark Brown wrote:
> On Thu, May 03, 2018 at 09:36:44PM +0000, Yixun Lan wrote:
>> From: Sunny Luo <sunny.luo at amlogic.com>
>> The SPICC controller in Meson-AXG SoC is capable of using
>> a linear clock divider to reach a much fine tuned range of clocks,
>> while the old controller only use a power of two clock divider,
>> result at a more coarse clock range.
>> Also convert the clock registeration into Common Clock Framework.
> This would be better split into two patches - one adding the new linear
> clock divider and the other one doing the CCF conversion. Splitting
> things out like that makes them much easier to review as each change is
> only doing one thing.
it's maybe obscure in my previous commit message, the clock divider
support is actually achieved via CCF framework, it can be split as two
I'm CCing clock mailing list (will do if I need to send a v2)
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