Applied "ASoC: meson: add axg tdm formatters DT bindings documentation" to the asoc tree

Mark Brown broonie at
Wed Jul 18 05:25:10 PDT 2018

The patch

   ASoC: meson: add axg tdm formatters DT bindings documentation

has been applied to the asoc tree at 

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>From 7713a70034f2cb54168d134ac523fdfcdda92a13 Mon Sep 17 00:00:00 2001
From: Jerome Brunet <jbrunet at>
Date: Tue, 17 Jul 2018 17:42:56 +0200
Subject: [PATCH] ASoC: meson: add axg tdm formatters DT bindings documentation

Add the DT bindings documentation for axg's TDM formatters: TDMIN

Signed-off-by: Jerome Brunet <jbrunet at>
Signed-off-by: Mark Brown <broonie at>
 .../sound/amlogic,axg-tdm-formatters.txt      | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt

diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt
new file mode 100644
index 000000000000..1c1b7490554e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/amlogic,axg-tdm-formatters.txt
@@ -0,0 +1,28 @@
+* Amlogic Audio TDM formatters
+Required properties:
+- compatible: 'amlogic,axg-tdmin' or
+	      'amlogic,axg-tdmout'
+- reg: physical base address of the controller and length of memory
+       mapped region.
+- clocks: list of clock phandle, one for each entry clock-names.
+- clock-names: should contain the following:
+  * "pclk"     : peripheral clock.
+  * "sclk"     : bit clock.
+  * "sclk_sel" : bit clock input multiplexer.
+  * "lrclk"    : sample clock
+  * "lrclk_sel": sample clock input multiplexer
+Example of TDMOUT_A on the A113 SoC:
+tdmout_a: audio-controller at 500 {
+	compatible = "amlogic,axg-tdmout";
+	reg = <0x0 0x500 0x0 0x40>;
+	clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
+		 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
+		 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
+		 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
+		 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
+	clock-names = "pclk", "sclk", "sclk_sel",
+		      "lrclk", "lrclk_sel";

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